Many current testing methods are used for integrated circuits with many microprocessor cores. In one technique, a single test is performed on each of the many (N) microprocessor cores at the same time and the test result is read from N output pin sets. In another conventional method, a single output pin set is used, but the test is repeated N times. It would be desirable to test the integrated circuit with multiple processor cores using a single test and using a single output pin set since a premium is placed on reducing the number of pin sets and reducing testing time.
Accordingly, there is a need for an improved method and device for testing multi-core processor integrated circuits.